block diagram features description rev.: f amendment: /0 issue date: october, 1998 the SY100S815 is a low skew 1-to-4 pecl differential driver designed for clock distribution in new, high- performance pecl systems. it accepts either a pecl clock input or a ttl input by using the ttl enable pin t en . when the ttl enable pin is high, the ttl input is enabled and the pecl input is disabled. when the enable pin is set low, the ttl input is disabled and the pecl input is enabled. the device is specifically designed and produced for low skew. the interconnect scheme and metal layout are carefully optimized for minimal gate-to-gate skew within the device. wafer characterization and process control ensure consistent distribution of propagation delay from lot to lot. since the s815 shares a common set of ?asic processing with the other members of the eclinps family, wafer characterization at the point of device personalization allows for tighter control of parameters, including propagation delay. to ensure that the skew specification is met, it is necessary that both sides of the differential output are terminated into 50 ? , even if only one side is being used. in most applications, all nine differential pairs will be used and, therefore, terminated. in the case where fewer than nine pairs are used, it is necessary to terminate at least the output pairs on the same package side (i.e. sharing the same v cco as the pair(s) being used on that side) in order to maintain minimum skew. quad pecl version of popular eclinps e111 low skew guaranteed skew spec ttl enable input selectable ttl or pecl clock input single +5v supply differential internal design pecl i/o fully compatible with industry standard internal 75k ? pecl input pull-down resistors available in 16-pin soic package clockworks SY100S815 final single supply quad pecl/ttl-to-pecl pin function e in , e in differential pecl input pair t in ttl input t en ttl input enable q 0 , q 0 ?q 3 , q 3 differential pecl outputs v cc pecl v cc (+5.0v) v ee pecl ground (0v) pin configuration pin names 1 2 3 4 5 6 7 8 15 16 14 13 12 11 10 9 v cc t in q 3 q 2 q 2 v cco e in t en v ee q 0 q 0 q 1 v cco top view soic z16-1 q 3 e in q 1 q 0 q 0 q 1 q 1 q 2 q 2 q 3 q 3 e in e in 0 1 t in t en 1
2 clockworks SY100S815 micrel v cc = v cco = +5.0v 5% t a = 0 ct a = +25 ct a = +85 c symbol parameter min. typ. max. min. typ. max. min. typ. max. unit i ih input high current 150 150 150 a i il input low current 0.5 0.5 0.5 a v ih input high voltage (1) 3.835 4.120 3.835 4.120 3.835 4.120 v v il input low voltage (1) 3.190 3.525 3.190 3.525 3.190 3.525 v v oh output high voltage (2) v cc 1025 v cc 955 v cc 870 v cc 1025 v cc 955 v cc 870 v cc 1025 v cc 955 v cc 870 mv v ol output low voltage (2) v cc 1890 v cc 1705 v cc 1620 v cc 1890 v cc 1705 v cc 1620 v cc 1890 v cc 1705v cc 1620 mv i cc power supply (3) 53 65 53 65 60 74 ma current pecl dc electrical characteristics notes: 1. v cc = v cco = 5.0v 2. v in = v ih (max.) or v il (min.) loading with 50 ? to v cc 2v. 3. all inputs and outputs open. truth table t en e in t in q llxl lhxh hxl l hxhh ttl dc electrical characteristics v cc = v cco = +5.0v 5% t a = 0 ct a = +25 ct a = +85 c symbol parameter min. typ. max. min. typ. max. min. typ. max. unit condition v ih input high voltage 2.0 2.0 2.0 v v il input low voltage 0.8 0.8 0.8 v i ih input high current (1),(2) 20 20 20 a 100 100 100 i il input low current (3) 0.6 0.6 0.6 ma v ik input clamp voltage (4) 1.2 1.2 1.2 v notes: 1. v in =2.7v 2. v in =5.0v 3. v in =0.5v 4. i in =-18 ma
3 clockworks SY100S815 micrel ac electrical characteristics (1?) notes: 1. part-to-part skew is defined as max. min. value at the given temperature. 2. the differential propagation delay is defined as the delay from the crossing points of the differential input signals to the crossing point of the differential output signals. 3. the single-ended propagation delay is defined as the delay from the 50% point of the input signal to the 50% point of the out put signal. 4. the within-device skew is defined as the worst case difference between any two similar delay paths within a single device. 5. v pp (min.) is defined as the minimum input differential voltage which will cause no increase in the propagation delay. the v pp (min.) is ac limited for the s815, as a differential input as low as 50mv will still produce full pecl levels at the output. 6. v cmr is defined as the range within which the v ih level may vary, with the device still meeting the propagation delay specification. the v il level must be such that the peak-to-peak voltage is less than 1.0v and greater than or equal to v pp (min.). v cc = v cco = +5.0v 5% t a = 0 ct a = +25 ct a = +85 c symbol parameter min. typ. max. min. typ. max. min. typ. max. unit t plh propagation delay to output (1) ps t phl e in (differential) (2) 430 630 430 630 430 630 e in (single-ended) (3) 330 730 330 730 330 730 t in 350 950 350 950 350 950 t skew within-device skew (4) 25 50 25 50 25 50 ps v pp minimum pecl (5) 250 250 250 mv input swing v cmr pecl common (6) 1.6 0.4 1.6 0.4 1.6 0.4 v mode range t r output rise/fall times 275 375 600 275 375 600 275 375 600 ps t f 20% to 80% ordering package operating code type range SY100S815zc z16-1 commercial SY100S815zctr z16-1 commercial product ordering code
4 clockworks SY100S815 micrel 16 lead soic .300" wide (z16-1) rev. 03 micrel-synergy 3250 scott boulevard santa clara ca 95054 usa tel + 1 (408) 980-9191 fax + 1 (408) 914-7878 web http://www.micrel.com this information is believed to be accurate and reliable, however no responsibility is assumed by micrel for its use nor for an y infringement of patents or other rights of third parties resulting from its use. no license is granted by implication or otherwise under any patent or pat ent right of micrel inc. ? 2000 micrel incorporated
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